■[TimeQuest][Quartus2] 制約ファイルの確認
▲cycloneIII_embedded_evaluation_kit_picture_viewer_settings.tcl
set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_adsc_n set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_bw_n set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_bwe_n set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_ce_n set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to ssram_oe_n set_instance_assignment -name TCO_REQUIREMENT "3.3 ns" -from * -to flash_ssram_a
SyncronusSRAMのアドレス，Byte enbale，ChipEnable，OutputEnableは3.3nSecのtCOを設定する．制御信号の全てのclockに対する出力遅延を定義している．（一定にそろえたい?）
set_instance_assignment -name TSU_REQUIREMENT "6 ns" -from * -to flash_ssram_d
SRAMのデータ用FFのSetupTimeを6nSecとしている？．
TCO_REQUIREMENTとTSU_REQUIREMENTを記述するのは，I/Oタイミング制約を課すことで，QuartusIIに対してレジスタつきI/Oピンの使用を促すためだろう*1．
▲cycloneIII_embedded_evaluation_kit_picture_viewer.sdc
他のところでも制約がある．SDCファイルで規定されているアレゲな何を理解する．参照するリファレンスは，主にTclScriptManual("TclScriptRefMnl.pdf")．
## Creating and setting variables for clock paths to make code look cleaner set System_Clock_int *|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0] set SSRAM_Clock_ext *|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] set Slow_Clock_int *|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[2] set Remote_Update_Clock *|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[3] set DDR_Local_Clock *|the_ddr_sdram|ddr_sdram_controller_phy_inst|alt_mem_phy_inst|ddr_sdram_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] set DDR_Controller_Clock *|the_ddr_sdram|ddr_sdram_controller_phy_inst|alt_mem_phy_inst|ddr_sdram_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0]
まずは，clockに対する制約を記述するため，clockコレクションを得るためのワイルドカード記述を定義している．名称の変更やPLLの出力端子番号等により変化するでしょう．
##SSRAM Constraints
set_output_delay -clock [get_clocks $SSRAM_Clock_ext] -reference_pin [get_ports {ssram_clk}] 2.4 [get_ports {ssram_adsc_n ssram_bw_n* ssram_bwe_n ssram_ce_n ssram_oe_n flash_ssram_a* flash_ssram_d*}]
set_input_delay -clock [get_clocks $SSRAM_Clock_ext] -reference_pin [get_ports {ssram_clk}] 4.1 [get_ports {flash_ssram_d*}]
set_multicycle_path -from [get_ports {flash_ssram_d*} ] -setup -end 2
starter kitのSSRAMは，"IS61LPS25636A"（8Mbit，36bit x 256k）です．ただしparity pbitは配線されていません．latency 2cycle，setup/holdは1.4/0.4[nSec]となっています．
制御信号等の出力遅延として，setup時間にマージンを1[nSec]加えて，2.4[nSec]としています（イメージ：ssram_clkに対して2.4nSec以上早く信号が出るように合成される）．
toeq(Output Enable to Output Valid)が3.1[nSec]なので，データの入力遅延としてマージンを1[nSec]とって，4.1[nSec]としている（イメージ：ssram_clkに対して，setup timeが4.1[nSec]加えられる．）．
## Cutting the paths between the system clock and ddr controller clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $Slow_Clock_int]
set_false_path -from [get_clocks $Slow_Clock_int] -to [get_clocks {osc_clk}]
## Cutting the paths between the system clock and ddr controller clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks $Slow_Clock_int] -to [get_clocks $System_Clock_int]
set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks $Slow_Clock_int]
## Cutting the paths between the system clock and ddr controller clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks $Slow_Clock_int] -to [get_clocks $DDR_Controller_Clock]
set_false_path -from [get_clocks $DDR_Controller_Clock] -to [get_clocks $Slow_Clock_int]
## Cutting the paths between the system clock and ddr controller clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $DDR_Controller_Clock]
set_false_path -from [get_clocks $DDR_Controller_Clock] -to [get_clocks {osc_clk}]
## Cutting the paths between the system clock and ddr controller clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks $DDR_Controller_Clock]
set_false_path -from [get_clocks $DDR_Controller_Clock] -to [get_clocks $System_Clock_int]
## Cutting the paths between the system clock and ddr local clock since there is a clock crossing bridge between them (FIFOs)
set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks $DDR_Local_Clock]
set_false_path -from [get_clocks $DDR_Local_Clock] -to [get_clocks $System_Clock_int]
## Cutting the paths between the external oscillator clock and the system clock since there is an asyncronous clock crosser between them
set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $System_Clock_int]
set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks {osc_clk}]
## Cutting the paths between the external oscillator clock and the system clock since there is an asyncronous clock crosser between them
set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $DDR_Local_Clock]
set_false_path -from [get_clocks $DDR_Local_Clock] -to [get_clocks {osc_clk}]
## Cutting the paths between the external oscillator clock and the remote update clock since there is an asyncronous clock crosser between them
set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $Remote_Update_Clock]
set_false_path -from [get_clocks $Remote_Update_Clock] -to [get_clocks {osc_clk}]
コメントにあるように，clock domain間に対してfalse pathを設定しています．
双方向に影響がないことを示すため，from/toを入れ替えて記述する必要があります．
また，clock5種全ての組み合わせが必要なわけではなく，あるmoduleを通してclockが隣接するものだけで良いです*2．
set_false_path -from [get_clocks tx_clk_to_the_tse_mac] -to [get_clocks $System_Clock_int] set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks tx_clk_to_the_tse_mac] set_false_path -from [get_clocks rx_clk_to_the_tse_mac] -to [get_clocks $System_Clock_int] set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks rx_clk_to_the_tse_mac] set_false_path -from [get_clocks tx_clk_to_the_tse_mac] -to [get_clocks $Slow_Clock_int] set_false_path -from [get_clocks $Slow_Clock_int] -to [get_clocks tx_clk_to_the_tse_mac] set_false_path -from [get_clocks rx_clk_to_the_tse_mac] -to [get_clocks $Slow_Clock_int] set_false_path -from [get_clocks $Slow_Clock_int] -to [get_clocks rx_clk_to_the_tse_mac]
Ethernet Phy-moduleのclockについて，false path設定を行っている模様（MAC-phyは追いかけてないのでスルー）．
#Constrain MAC network-side interface clocks create_clock -period "125 MHz" -name tx_clk_to_the_tse_mac [ get_keepers HC_TX_CLK] create_clock -period "125 MHz" -name rx_clk_to_the_tse_mac [ get_keepers HC_RX_CLK]
（MAC-phyは追いかけてないのでスルー）．
#Constrain timing for half duplex logic set_multicycle_path -setup 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_keepers *] set_multicycle_path -setup 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_keepers *] set_multicycle_path -setup 4 -from [ get_keepers *] -to [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] set_multicycle_path -setup 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|half_duplex_ena_reg2] -to [ get_keepers *] set_multicycle_path -hold 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_keepers *] set_multicycle_path -hold 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_keepers *] set_multicycle_path -hold 4 -from [ get_keepers *] -to [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] set_multicycle_path -hold 4 -from [ get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|half_duplex_ena_reg2] -to [ get_keepers *] set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*] set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*] set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_keepers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
（MAC-phyは追いかけてないのでスルー）．
